Measurement-computing CIO-DAS160x/1x Manual do Utilizador descarregar pdf (Página 29)

BL3 to BL0 = BURST LENGTH. This nibble determines the number of conversions per trigger when in

the burst mode. There are one to sixteen samples (single-ended) or eight samples (differential) in a burst.

When the CIO-DAS1600 is not in the burst mode these bits have no function.

CTR0 = 1. When CTR0 = 1, an onboard 100 kHz clock signal is ANDed with the COUNTER 0 CLOCK

INPUT (pin 21). A high on pin 21 will allow pulses from the onboard source into the 8254 Counter 0

input. (This input has a pull-up resistor on it, so no connection is necessary to use the onboard clock as a

pacer clock.

CTR0 = 0. When CTR0 = 0, the input to 8254 Counter 0 is entirely dependent on pulses at pin 21,

COUNTER 0 CLOCK INPUT.

TRIG0 = 1. When TRIG0 = 1 external gating of the pacer clock at pin 25 is enabled. Pin 25 going high

will enable the pacer. The input at pin 25 is connected to a pull-up resistor and will remain high unless

pulled low externally.

TRIG0 = 0. When TRIG0 = 0, the gating of the pacer clock at pin 25 is disabled. The gates of counter 1

& 2 are held high, preventing external control of the pacer gate.

Figure 6-1 may help you understand these registers. They are further explained in literature covering the

8254.

Figure 6-1. Pacer Clock Block Diagram

COUNTER 0

COUNTER 2

COUNTER 1

A/D PACER

+5V

10K

+5V

10K

10 MHz

1 /10

CONTROL REGISTER

BASE + 10

TRIG

CTR0

GATE

OUT

10 MHz

1MHz

+5V

10K

CIO-DAS1600 8254 PACER CLOCK & CONTROL

CTR 2 OUT

CTR 0 OUT

TRIGGER

GATE 0

CTR 0 IN

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 43 44

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