Measurement-computing CIO-DAS160x/1x Manual do Utilizador descarregar pdf (Página 28)

6.1.7 DMA, INTERRUPT & TRIGGER CONTROL

BASE ADDRESS + 9

TS0TS1DMAXIR0IR1IR2INTE

01234567

A read and write register.

READ

INTE = 1, Interrupts are enabled. An interrupt generated will be placed on the PC bus interrupt level

selected by IR4, IR2 & IR1. INTE = 0, interrupts are disabled.

IR2, IR1, IR0 are bits in a binary number between 0 and 7 which map interrupts onto the PC bus interrupt

levels 2 to 7. Interrupts 0 and 1 cannot be asserted by the CIO-DAS1600.

Table 6-2. Interrupt Program Codes

7111

6011

5101

4001

3110

2010

None100

None000

INTERRUPT LEVELIR0IR1IR2

When DMA = 1, DMA transfers are enabled.

When DMA = 0, DMA transfers are disabled.

Note that this bit only allows the CIO-DAS1600 to assert a DMA request to the PC on the DMA request

level selected by the DMA switch on the CIO-DAS1600. Before this bit is set to 1, the PC's 8237 (or

appropriate) DMA controller chip must be set up.

TS1 & TS0 control the source of the A/D start conversion trigger according to Table 6-3 below.

Table 6-3. Source Codes for the A/D Start Conversion Trigger

Start on Pacer Clock Pulse (CTR 2 OUT, no external access)11

Start on rising edge (Digital input 0, Pin 25)01

Software triggered A/D onlyX0

TS0TS1

6.1.8 PACER CLOCK CONTROL REGISTER

BASE ADDRESS + Ah

TRIG0CTR0XXBL0BL1BL2BL3

01234567

Write only

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 43 44

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