Measurement-computing CIO-DAS16/330 Manual do Utilizador descarregar pdf (Página 14)

4.4 A/D DATA & CHANNEL REGISTERS

Note: When in enhanced mode, the bus interface is 16 bits wide and BASE +0 and BASE +1 should be read as a 16 bit

pair. To whit, the register at BASE + 1 should be read as the most significant eight bits of a 16-bit read to BASE + 0.

BASE ADDRESS

CH1CH2CH4CH8A/D12

LSB

A/D11A/D10A/D9

01234567

A read/write register.

READ

On read, it contains two types of data. The least significant four digits of the analog input data and the associated

channel number.

These four bits of analog input data must be combined with the eight bits of analog input data in BASE + 1, forming

a complete 12-bit number. The data is in the format 0 = minus full scale. 4095 = +FS.

The channel number is binary. The weights are shown in the table above. If the current channel were 5, then bits

CH4 and CH1 would be high, CH8 and CH2 would be low.

WRITE

Writing any data to the register causes an immediate A/D conversion.

BASE ADDRESS +1

A/D8A/D7A/D6A/D5A/D4A/D3A/D2A/D1

MSB

01234567

A Read-only register.

On read, the most significant A/D byte is read.

4.5 CHANNEL MUX SCAN LIMITS REGISTER

BASE ADDRESS +2

CH L1CH L2CH L4CH L8CH H1CH H2CH H4CH H8

01234567

A read and write register.

READ

The current channel scan limits are read as one byte. The high channel number scan limit is in the most significant

four bits. The low channel scan limit is in the least significant four bits.

WRITE

The channel scan limits desired are written as one byte. The high channel number scan limit is in the most significant

four bits. The low channel scan limit is in the least significant four bits.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 33 34

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Measurement-computing CIO-DAS16/330 Manual do Utilizador Página 14