Measurement-computing CIO-DAS08-AOH Manual do Utilizador descarregar pdf (Página 18)

6.6 COUNTER CONTROL REGISTER

BASE ADDRESS + 7 (Write Only)

BCDM0M1M2RL0RL1SC0SC1

01234567

WRITE

SC1 to SC0 are the counter select bits. They are binary-coded between 0 and 2.

RL1 to RL0 are the read and load control bits:

Read/load low the high byte (Word Transfer)11

Read/load low byte01

Read/load high byte10

Latch counter00

OPERATIONRL0RL1

M2 to M0 are the counter control operation type bits:

Hardware triggered strobe101

Software tirggered strobe001

Square wave genrator110

Rate generator010

Programmable one-shot100

Change on terminal count000

OPERATION TYPEM0M1M2

BCD = 0 then counter data is 16 bit binary. (65,535 max)

BCD = 1 then counter data is 4 decade Binary Coded Decimal. (9,999 max)

6.7 COUNTER TIMER OPERATION

The 8254 counter timer chip (Figure 6-1) can be used for event counting, frequency and pulse measurement and as a pacer

clock for the A/D converter. All the inputs, outputs, and gates of the counter are accessible through the 37-pin analog

connector with the exception of the counter 2 input.

The counter is easy to understand. The GATE line determines whether or not TTL level pulses present at the CLK input will

decrement the counter. The OUT line then transitions (pulses or shifts) depending on the codes in the control register and the

count value in the count register.

The counter gates, inputs and outputs are all simple TTL.

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 31 32

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Measurement-computing CIO-DAS08-AOH Manual do Utilizador Página 18