Measurement-computing ADAC/5500 Series Manual do Utilizador descarregar pdf (Página 46)

Acceptable Operating Limit

Signal Plus Common Mode: ±12 V

Output Coding

Unipolar: Straight binary

Bipolar: Offset binary 2's complement

Data Format: 16-bit right justified

6.1.2 A/D Trigger - ADAC/5500MF

Clock Sources: - software

- on board programmable pacer

- user defined external TTL

External Clock Input Delay: - 100ns uncertainty

Trigger Sources: - software

- on board pacer (burst mode)

- external (TTL)

Triggering Modes: - software gate

- external gate

- periodic burst

- pre-trigger (sample until trigger)

- post-trigger (sample after trigger)

- about-trigger (sample before and after trigger)

External Trigger Input Delay: - 100ns uncertainty

6.1.3 Digital Inputs / Outputs – ADAC/5500MF

Number: 16

I/O Direction Select: Software selectable in groups of eight

Inputs are unlatched read-only.

Data Coding: Positive logic

Input Level: 5 V CMOS/TTL with 4.7 Kohm pull-up resistor

High Level Input Voltage: 2 V min.

Low Level Input Voltage: 0.8 V max.

High Level Output Voltage: 2.4 V

Low Level Output Voltage: 0.5 V

Maximum Output Current: Low: 24 mA (sinking)

High: 24 mA (sourcing)

ADAC Series 908196 -41- ADAC/5500 Series User’s Manual

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Measurement-computing ADAC/5500 Series Manual do Utilizador Página 46