Measurement-computing PCM-DAC08 Manual do Utilizador descarregar pdf (Página 19)

WRITE: D/A Data can be written to this address and to Base + 1 to form a 12 bit D/A

data word. All 8 DAC’s are updated using this register. The DAC being updated is

set via the Select bits (S3 to S0) in the Base +2 register.

READ: Starts a D/A conversion, updates the output of the selected DAC.

D/A0D/A1D/A2D/A3D/A4D/A5D/A6D/A7

01234567

BASE + 1 - DAC Value MSB (4 bits)

WRITE: Send DAC data.

READ: Clear Interrupt Request bit at Base +4 bit D#3

D/A8D/A9D/A10D/A11D/A12XXX

01234567

BASE + 2 - DAC Select Register

WRITE: Set the DAC to update

READ: Read back current DAC updating

D/A0D/A1D/A2D/A3D/A4D/A5D/A6D/A7

01234567

Update all 8 DACs simultaneously. No write function.XXX1

Latch new D/A value for DAC7Update DAC 6 & 71110

Latch new D/A value for DAC6Update DAC 6 & 70110

Latch new D/A value for DAC5Update DAC 4 & 51010

Latch new D/A value for DAC4Update DAC 4 & 50010

Latch new D/A value for DAC3Update DAC 2 & 31100

Latch new D/A value for DAC2Update DAC 2 & 30100

Latch new D/A value for DAC1Update DAC 0 & 11000

Latch new D/A value for DAC0Update DAC 0 & 10000

FUNCTION WRFUNCTION RDS0S1S2S3

Note that DACs are always updated in pairs. For example, if you latch new data to

DAC1, then update the DAC0 and DAC1 pair, DAC1 updates with the new value and

DAC0 updates with the same value as before since the latch (data for output) has not

changed.

CLR: Setting the CLR bit to 1 resets all 8 DACs output to 0V. Default and normal

operation is CLR=0, which has no effect on the DAC outputs.

BASE + 3 - Digital I/O (8 bits)

WRITE: Updates output of DIO bits set for output.

READ: Reads current status of DIO bits for input. Reads back output state of DIO

bits set for output.

1 2 ... 14 15 16 17 18 19 20 21 22 23

Sem comentários

Measurement-computing PCM-DAC08 Manual do Utilizador Página 19